1. Field of the Invention
The present invention relates to an output buffer circuit, especially relates to an output buffer circuit embedded in a semiconductor integrated circuit.
2. Description of the Related Art
The semiconductor integrated circuit called as SOG (Sea Of Gate) type has many input buffer circuits and output buffer circuits. The output buffer circuit is connected to an output terminal and drives an external load connected to the output terminal to H level or L level. When a plurality of output buffer circuits drive the external loads to H level or L level simultaneously, current which flows to the semiconductor integrated circuit changes sharply. Noise occurred by rapid change of the current flow may affect other circuits, such as the input buffer circuit. For example, the input buffer circuit in the semiconductor integrated circuit may cause incorrect operation.
As conventional technology for solving such a problem, an output buffer circuit that has a threw-rate control function is known. The threw-rate means the change speed of an output voltage output from the output buffer circuit. In such a conventional output buffer circuit, since the threw-rate is controlled, rapid change of the current flow explained above is controlled and thus occurrence of the noise is reduced.
One technology for controlling the threw-rate is that a dimension of a MOS transistor comprised of a pre-driver, which drives a MOS transistor comprised of a main driver, is set small. However, in this approach, since the drive capability of the MOS transistor becomes small, although it is effective in reduction of a noise, the propagation delay time of the output buffer circuit may become long.
Another technology for controlling the threw-rate is providing a resistance means in the pre-driver. An output buffer circuit which has the pre-driver to which the resistance means is added is described in FIG. 1 and FIG. 4 of U.S. Pat. No. 5,120,992. However, since this approach only adds the resistance means, although it is effective in reduction of the noise, the propagation delay time of the output buffer circuit may become long.
An output buffer circuit that has a PMOS transistor and an NMOS transistor which are connected in parallel (called as a transmission gate) and used as the above-mentioned resistance means is described FIG. 1 and FIG. 4 of Japanese Laid Open Patent No. 5-218847. However, since a gate electrode of the PMOS transistor and a gate electrode of the NMOS transistor are connected to a ground potential and a power supply potential, respectively, the threw-rate is determined only by the ON resistance of the PMOS transistor and the NMOS transistor. That is, this approach means that flexibility is small in control of the threw-rate.
An output buffer circuit having a control circuit for controlling the conductive states of the PMOS transistor and the NMOS transistor connected in parallel and mentioned above is described in FIG. 1 of Japanese Laid Open Patent No.10-290154.
In this approach, a rising transition time period where the output voltage of the output buffer circuit rises from L level to H level can be decreased by setting up the ON resistance of the PMOS transistor lower than the ON resistance of the NMOS transistor. However, a falling transition time period where the output voltage falls from H level to L level in this case increases conversely. On the other hand, the falling time period can be decreased by setting up the ON resistance of the NMOS transistor smaller than the ON resistance of the PMOS transistor. However, the rising time period in this case increases conversely. That is, it is difficult to improve more the propagation delay time of the whole output buffer circuit in this approach.
As mentioned above, the problem of a noise and the problem of propagation delay time are in the relation of a trade-off. Therefore, the output buffer circuit that overcomes two problems in the relation of the trade-off has been demanded.
It is an object of the present invention is to provide an output buffer circuit for overcoming two problems in the relation of an above-mentioned trade-off.
In detail, it is an object of the present invention is to provide an output buffer circuit that can reduce a propagation delay time and can reduce a noise. It is another object of the present invention is to provide an output buffer circuit that has good slew-rate controllability.
According to one aspect of the present invention, for achieving one or more of the above objects, there is provided an output buffer circuit which includes a power supply node supplied with a power supply potential level, a ground node supplied with a ground potential level, and a data output node which outputs data. The output buffer circuit also includes a first transistor of a first conductive type, which is coupled between the power supply node and the data output node and which has a control electrode, a second transistor of a second conductive type, which is coupled between the ground node and the data output node and which has a control electrode, and a data input node which receives data. The output buffer further includes a first pull up transistor of the first conductive type, which is provided at a first current path between the power supply node and the control electrode of the first transistor and which charges the control electrode of the first transistor to the power supply potential level in response to data at the data input node, a first pull down transistor of the second conductive type, which is provided at a second current path between the ground node and the control electrode of the first transistor and which discharges the control electrode of the first transistor to the ground potential level in response to data at the data input node, a second pull up transistor of the first conductive type, which is provided at a third current path between the power supply node and the control electrode of the second transistor and which charges the control electrode of the second transistor to the power supply potential level in response to data at the data input node, and a second pull down transistor of the second conductive type, which is provided at a fourth current path between the ground node and the control electrode of the first transistor and which discharges the control electrode of the first transistor to the ground potential level in response to data at the data input node. The output buffer circuit also includes a slew-rate control node, a third transistor of the first conductive type, which is coupled between the power supply node and the slewrate control node and which has a control electrode connected to the control electrode of the first transistor, a fourth transistor of the second conductive type, which is coupled between the ground node and the slew-rate control node and which has a control electrode connected to the control electrode of the second transistor, a first variable resistance circuit which is provided at the second current path and which has a resistance value, the resistance value is changed in response to a potential of the slew-rate control node, and a second variable resistance circuit which is provided at the third current path and which has a resistance value, the resistance value is changed in response to a potential of the slew-rate control node.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.